1. Field
The present invention relates to a clock generating circuit and method, and more particularly, to an internal clock generating circuit and method to generate an internal clock signal with a data signal.
2. Description of the Related Art
Most semiconductor chips include an internal clock to generate an internal clock signal. The internal clock signal is used as a reference signal for controlling various internal signals in appropriate timing, so that the data, which is externally supplied, can be processed in appropriate ways.
Most of conventional internal clock generating circuits include a phase-locked loop
(PLL) or a delay-locked loop (DLL) to generate the internal clock signal. The conventional internal clock generating circuits receive an external clock signal. And, the external clock signal is locked with the PLL or the DLL to generate the internal clock signal.
However, in the conventional internal clock generating circuits, an extra signal line is required for receiving the external clock signal. The extra signal line causes the constitution of the internal clock generating circuit to be more complicated. And, in the conventional internal clock generating circuits, an extra locking time is required for locking the extra clock signal. The extra locking time causes the operating speed of the internal clock generating circuit to be declined.